Non-volatile transistor memory array incorporating read-only elements with single mask set

ABSTRACT

A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width dimensions. In the mask set for EEPROMs a principal mask is used for formation of a depletion implant. In the case of one type of read-only memory element, this mask is mainly blocked, leading to formation of a transistor with a non-conductive channel between source and drain. In the case of another read only memory element, the same mask is unblocked, leading to formation of a transistor with a highly conductive or almost shorted channel between source and drain. These two read only memory elements are designated as logic one and logic zero. By having rows of read-only memory elements with rows of EEPROMs on the same chip, a more versatile memory array chip may be built without sacrificing chip space.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of pending U.S. patent application Ser. No.10/810,035 filed Mar. 26, 2004.

TECHNICAL FIELD

The invention relates to manufacturing a semiconductor memory arrayhaving non-volatile and read only memory devices.

BACKGROUND ART

Many complex microcircuits, especially those employing internalmicrocontrollers, have a need for non-volatile memory in which to storecritical data. Typically this data consists of operating instructionsfor a microcontroller, although it may also consist of other criticaldata such as keys or configuration data. The development of this data isfrequently a lengthy task, with the data not fully debugged until aftera microcircuit is developed. Once this data is fully developed, it isoften desirable to make the data permanent. There are several reasonsfor this. A first reason is that the overall security of the system maybe compromised if the data can be altered. Another reason relates toreduction of manufacturing cost. The time required to program eachmicrocircuit can be eliminated from the manufacturing cycle ifprogramming resides in pre-programmed read only memory devices. A thirdreason relates to reliability of the data. Many non-volatile memoryarrays are susceptible to environmental effects, such as temperature orradiation, which could disturb the data. An object of the invention isto provide a semiconductor memory array having mostly non-volatilememory cells but with permanently written data in portions of the memoryarray.

SUMMARY OF THE INVENTION

Within a non-volatile transistor memory element, specifically an EEPROMcell, there is typically a depletion implant in a MOS or CMOS processused to provide conduction in areas not under the control of polysilicongates. This depletion implant is established by a mask or masks in themanufacturing process used to define the areas within the cell thatreceive the implant. The present invention makes use of this maskmodified to provide programming data to a ROM cell. The depletionimplant is either substantially removed from the cell (for a MOStransistor structure with no channel between source and drainelectrodes, thereby designating a 0) or extending all the way under thecell (for a shorted channel between the source and drain, therebydesignating a 1). The presence or absence of the depletion implant isall that is required to determine the state of the bit.

In addition, for permanently written memory cells, masks that define thefloating polysilicon gate and the feature that defines the thin tunneloxide are not needed. By blocking formation of these two layers thecells lose the ability to be changed by standard EEPROM programmingtechniques.

This invention allows the same EEPROM mask set to be used as a ROM maskof the same footprint on a selected basis, for example, a row-by-rowbasis. The unaltered rows would continue to function as an EEPROM. Thischange can be made without any redesign of the existing microcircuitmask set or even the EEPROM mask set itself, or the manufacturingprocess.

In other words, essentially the same set of masks can be used to formall transistors, both non-volatile memory elements and read-only memoryelements with blocking or non-use on the one hand or opening of somemask portions on the other hand, thereby leading to the same footprintfor all transistors in a memory array. Use of the same footprint leadsto greater geometric regularity in the array topology and theopportunity to achieve greater functionality in a memory array that hasthe same dimensions as one without the enhanced functionality.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a non-volatile memory transistor device inaccordance with the invention.

FIG. 2 is a side sectional view of the device of FIG. 1 taken alonglines 2-2.

FIG. 3 is a top plan view of a first read-only memory transistor devicein accordance with the invention.

FIG. 4 is a side sectional view of the device of FIG. 3 taken alonglines 4-4.

FIG. 5 is a top plan view of a second read-only memory transistor devicein accordance with the invention.

FIG. 6 is a side sectional view of the device of FIG. 5 taken alonglines 6-6.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to FIGS. 1 and 2, an EEPROM cell is shown having length Land width W dimensions, with an areawise footprint L×W. Such a cellwould normally be a single element in an memory array having “n” rowsand “m” columns where “n” and “m” are integers.

A p-type wafer has memory cells that are laid out by first establishingan active area 11, indicated by stippling in FIG. 1 and defined by amask. The active area is seen to have longitudinal or lengthwise axis,parallel to line L, but running through the entire length of the activearea. The active area is lightly doped and will contain source and drainimplants for two MOS transistors.

Next, a buried n-diffusion is established in regions 13 and 15,indicated by forward-slant hatching. This is a heavily doped n+region inthe substrate 29 suitable for forming electrodes. Region 13 forms partof drain 23 in FIG. 2 and n-diffusion region 15 forms part of source 25in an EEPROM transistor 27. Between the subsurface drain 23 and source25 is a channel established by electric fields that are set up betweensource, drain and gate.

Above the substrate 29 is a first conductive polysilicon layer 31, knownas “poly I”, seen by reverse line hatching in FIGS. 1 and 2. Below thepoly I layer, a layer of thin oxide exists sometimes called “tunneloxide” with a window defining a polysilicon “dip-down” feature 33 usedto facilitate tunneling. The tunnel oxide layer is thinnest below thedip-down feature 33, and above the substrate, frequently requiring anumber of masks to define feature 33 within the thin oxide layer. Atopthe thin tunnel oxide layer and merged with the tunnel oxide is gateoxide insulatively separating the poly I layer 31 from the substrate 29.The poly layer 31 may have optional nitride spacers 35 protecting thepoly I layer from peripheral charge leakage or contamination.

A source region 39 in FIG. 2 can be an ion implanted zone, together withthe left side 37 of shared drain 23, also an ion implanted region forforming a sense transistor 41. A second polysilicon layer 43, poly II,spaced over the substrate 29 by gate oxide above substrate 29, can serveas an alignment tool for implanting ions into substrate 29 to formsource 39 and drain 37. In the EEPROM transistor 27 the poly II layer 43resides atop the poly I layer 31.

Note that the width dimension, W, of the select transistor 41 appears tobe the same as the width dimension of the EEPROM transistor 27 such thatthe overall dimensions of the cell appear to be generally rectangularhaving dimensions L×W. This need not be the case and generally would notbe the case. Slight differences in width exist. A contact 45 allowsexternal communication with drain 39. Communication with otherelectrodes may be made be stripe-like conductive paths (not shown)through these electrodes, or by other techniques well known in the art.

In FIGS. 3 and 4, a read-only memory device 51 and select transistor 53is shown having the same L×W dimensions as the EEPROM and selecttransistor of FIGS. 1 and 2. The active area 11 is defined by the samemasks as in FIGS. 1 and 2. Similarly, the poly II layers 43 are in thesame relation in the top view of FIG. 3, although the right hand poly IIlayer is lower in FIG. 4 because there is no poly I layer beneath it asin the EEPROM of FIG. 1. There is a buried n-diffusion 15 on the rightside of the device giving rise to source 25 but there is no conductivepath to drain 55. The select transistor 53 will always sense an opencircuit because the channel between source 25 and drain 55 ispermanently open. The memory device of FIG. 3 is thus a read only memoryhaving a particular memory state, for example a logic zero. Inmanufacturing the device in FIGS. 3 and 4, it should be noted that theburied n-diffusion region 15 is very limited. This means that the maskfor forming the n-diffusion is blocked to protect most of the substratefrom the n-diffusion, a change relative to FIGS. 1 and 2. Moreover,masks for forming the tunnel oxide region and the poly I region are notemployed. The mask for forming the poly II region remains the same.

In FIGS. 5 and 6, a read-only memory device 61 and select transistor 53are shown having the same combined L×W dimensions as the EEPROM andselect transistors of FIGS. 1 and 2 and the same combined dimensions asthe read-only memory device and select transistor of FIGS. 3 and 4. Theactive area 11 is defined by the same mask as in FIGS. 1-4. Similarly,the poly II layers 43 are the same as in FIG. 4. The principaldifference between FIG. 5 and FIG. 3 is that the buried n-diffusion 65extends longitudinally across the memory cell 61 completely under thepoly II layer 43, essentially forming a subsurface conductive layerunder the poly II layer and merging the source electrode 65 with theless heavily doped drain electrode 55. The select transistor 53 in FIG.6 has a source 69, a gate 43 made of poly II layer material and a shareddrain 55. Select transistor 53 senses a permanently shorted read-onlymemory transistor 61 with the channel region always shorting drain 55 tosource 65.

In the manufacture of the device of FIGS. 5 and 6, the mask for makingthe buried-n layer is unblocked, making the buried n-diffusion region ofsource 65 large, extending completely under the gate 43, a poly II layerportion. The select transistor 53 will always sense a closed circuit,i.e. low resistance, because the channel dimension between source anddrain is reduced. The read-only memory device of FIG. 5 is assigned theopposite memory state as the device of FIG. 3, i.e. a logic one. Themasks for making the device of FIG. 5 are the same as the masks formaking the device of FIG. 3, except that the buried n-diffusion mask ismodified as described.

In operation, it is necessary to separate rows of ROM memory from EEPROMmemory in a group. For such rows, the poly II control gate 43 is tiedlow to keep the “zero” cells turned off. While most transistors in anarray will be ROM memory transistors, several rows of EEPROM memoryelements, i.e. a second group of rows, can be provided. Within each rowof ROM cells, the programming of ones and zeros may be intermixed. Sincethe footprint for all devices is the same, different memory chips canhave a different configuration of read-only memory elements, yet thechip topology will be the same.

1. A method of making a transistor memory array with both read-only memory and rewriteable MOS and CMOS memory transistors, all having subsurface electrodes and channels comprising: providing a single mask set for forming a memory array of rows and columns of memory transistor sites, at least including masks for forming a subsurface active region, heavily doped first and second, spaced apart depletion implant subsurface regions in the active region defining a channel therebetween, a thin oxide layer, a first polysilicon layer and a second polysilicon layer spaced apart from and over the first polysilicon layer; for a first set of memory transistor sites, blocking mask portions for forming the second depletion implant subsurface region to the extent that the channel is extended to impede transistor conductivity, the mask set further modified by blocking formation of the thin oxide layer and the first polysilicon layer, thereby forming read-only memory transistor cells that are open at the first set of sites; for a second set of memory transistor sites, increasing the first and second depletion implant subsurface regions to an extent that the channel is shorted to establish permanent transistor conductivity at the second set of sites, the mask set further modified by blocking formation of the thin oxide layer and the first polysilicon layer; and for a third set of memory transistor sites, using the single mask set to form EEPROM memory transistor cells.
 2. The method of claim 1 further defined by grouping the first and second sets of memory transistor sites in a first group of rows and grouping the EEPROM memory transistors in a second group of rows.
 3. The method of claim 1 further defined by establishing an active region using the single mask set and forming a select transistor adjacent to the memory transistor.
 4. The method of claim 3 further defined by forming the active region as a longitudinal region with opposed edges, the active region having buried n subsurface regions for at least the memory transistors.
 5. A method of making a transistor memory array comprising: establishing an array with rows and columns of memory cells, each cell having an active area of a specified longitudinal dimension sufficient in length for formation of both a non-volatile memory cell and a read-only memory cell.
 6. The method of claim 5 wherein the memory array comprises rows and columns of transistor cells with a first plurality of rows of non-volatile memory cells and a second plurality of read-only memory transistor cells.
 7. The method of claim 5 further defined by forming a select transistor within the active area for both non-volatile memory transistor cells and read-only memory transistor cells.
 8. The method of claim 5 further defined by providing two poly layers for the plurality of non-volatile memory transistor cells and a single poly layer for the read-only memory transistor cells.
 9. The method of claim 6 further defined by programming the read-only memory transistor cells at the time of manufacture with pre-defined data consisting of ones and zeros.
 10. The method of claim 2 further defined by forming the EEPROM memory transistors with floating gates.
 11. A method of making a semiconductor memory array comprising: designing a single mask set for a plurality of diverse memory cell types to reside on a common wafer, selecting first masks from said single mask set for building a plurality of EEPROM memory cells, selecting second masks from said single mask set for building a plurality of read only memory cells having a first logic state, and selecting third masks from said single mask set for building a plurality of read only memory cells having a second logic state.
 12. The method of claim 11 wherein said memory cells all have the same areawise dimensions.
 13. The method of claim 11 further defined by providing a select transistor and a memory transistor in each memory cell.
 14. The method of claim 13 further defined by providing first and second spaced apart source electrodes in each memory cell with an intervening drain electrode.
 15. The method of claim 14 further defined by providing a first source electrode and said drain electrode to the memory transistor and a second source electrode and said drain electrode to the memory transistor in each memory cell.
 16. The method of claim 14 further defined by providing a tunnel oxide window to EEPROM memory cells above said drain electrode.
 17. Method of making a semiconductor memory array comprising: establishing active areas of identical length and width dimensions in rows in a semiconductor wafer substrate, upon a first row of active areas of the semiconductor wafer substrate, building EEPROM memory cells in said active areas, upon a second row of active areas of the semiconductor wafer substrate, building read only memory cells that have a permanent memory characteristic of a first logic state in said active areas, and upon a third row of active areas of the semiconductor wafer substrate, building read only memory cells that have a permanent memory characteristic of a second logic state in said active areas.
 18. The method of claim 17 further defined by fabricating a select transistor in each active area.
 19. The method of claim 18 further defined by fabricating floating gates for said EEPROM memory cells having floating gates made from a first polysilicon layer, fabricating an adjacent select transistor from a second polysilicon layer and fabricating control gates for said EEPROM cells from the second polysilicon layer.
 20. The method of claim 17 further defined by building the read only memory cell with the first logic state established by an electrically shorted channel in a memory transistor of the memory cell.
 21. The method of claim 17 further defined by building the read only memory cell with the second logic state established by an electrically open channel in a memory transistor of the memory cell.
 22. The method of claim 17 further defined by building the read only memory cells having implanted source and drain electrodes of a first dimension for establishing the first logic state and having implanted source and drain electrodes of a second dimension for establishing the second logic state.
 23. A method of making a semiconductor memory array comprising: establishing uniform length and width dimensions of memory cells in an array, each cell having a memory transistor and a select transistor in adjacent active areas of a common substrate, forming first memory cells of the array as EEPROM transistors, forming second memory cells of the array as ROM transistors in a second logic state, forming third memory cells of the array as ROM transistors in a second logic state, whereby the first, second and third memory cells all have the same length and width dimensions.
 24. The method of claim 23 wherein said EEPROM transistors are formed as floating gate transistors.
 25. The method of claim 23 wherein said ROM transistors are MOS transistors.
 26. The method of claim 23 wherein the first memory cells are in first rows of the memory array and the second and third memory cells are in second rows of the memory array.
 27. The method of claim 24 further defined by fabricating spacers on opposite sides of said floating gates.
 28. The method of claim 26 further defined by fabricating memory cells in the second rows with spaced apart source and drain electrodes having no conductive path therebetween such that no channel can be formed between source and drain electrodes.
 29. The method of claim 26 further defined by fabricating memory cells in the third row with spaced apart source and drain electrodes having a permanent conductive path therebetween such that a channel between source and drain electrodes forms the permanent conductive path. 